1. Field of the Invention
This invention relates to a semiconductor nonvolatile storage (device) and a method of fabricating the same, particularly to a semiconductor nonvolatile storage writable only once by breakdown of a memory oxide film provided between a gate electrode and a memory gate electrode and a method of fabricating the same.
2. Description of the Related Art
In semiconductor integrated circuits, product yield and performance stability are improved by storing in a once-only writable memory device correction for variance in transistor threshold voltage during production, change in operating conditions or the like.
This type of memory device is also utilized, for example, in a frequency error compensation circuit used in an oscillator circuit which generates a constant frequency signal.
Such once-only writable memory devices include PROMs (Programmable Read Only Memories) of, among others, the laser fusing, electrical fusing and junction breakdown types.
The laser fusing PROM is high in cost because it needs a laser beam source for the data write operation and requires a window for entry of the laser beam to be formed in the passivation film (protective film) covering the fuse. Another disadvantage is low mounting freedom owing to the need to conduct writing after mounting.
The electrical fusing PROM involves physical breakdown of polysilicon and therefore entails problems such as silicon fragment occurrence and passivation film degradation.
The junction breakdown PROM uses a current of at least 100 mA for the data write operation. Since this requires application of a high voltage that the semiconductor device must be capable of withstanding, the production process is complex and connection to other devices is not possible.
To overcome these problems, Japanese patent laid-open publication No. 8-288468, for example, teaches a nonvolatile semiconductor device wherein silicon fragment contamination and passivation film degradation do not occur, increased breakdown voltage is not required, and a once-only write is also possible after mounting.
This nonvolatile semiconductor device is configured to enable a once-only write by breaking down a memory oxide film provided between a gate electrode and a memory gate electrode provided on a field oxide film on the semiconductor substrate.
In the fabrication of this type of semiconductor device, the trend toward thinner gate oxide films, memory oxide films and the like make securement of dry etching conditions having a sufficient selectivity ratio with respect to the oxide film an important issue where the purpose is damage-free processing of the gate electrodes.
As an effective means for securing a sufficient selectivity ratio with respect to the oxide film in the processing of gate electrodes, dry etching using hydrogen bromide (HBr) as etching gas is widely adopted.
In dry etching using hydrogen bromide as etching gas, however, since bromide occurring during etching on the wafer surface remains as a residual reaction product, treatment with a hydrofluoric acid (HF) aqueous solution is necessary for its removal.
Therefore, at the time of fabricating a semiconductor nonvolatile storage wherein writing is effected by breaking down a thin memory oxide film formed between a gate electrode and a memory gate electrode, whose material is polycrystalline silicon, (hereinafter also called an "inter-gate insulating film breakdown type memory"), the hydrofluoric acid aqueous solution treatment causes etching of the memory oxide film in the lateral direction simultaneously with its exposure.
As a result, unnecessary current flows between the gate electrode and the memory gate electrode, possibly making normal operation as a semiconductor nonvolatile storage unattainable.
The method of fabricating an inter-gate insulating film breakdown type memory that is a semiconductor nonvolatile storage of this type according to the prior art will now be explained with reference to FIGS. 21 to 29.
FIGS. 21 to 29 are sectional views showing in order the steps of the conventional method of fabricating an inter-gate insulating film breakdown type memory.
First, as shown in FIG. 21, a field oxide film 2 is formed on the surface of a semiconductor substrate 1 of N-type conductivity.
Next, as shown in FIG. 22, the surface of the semiconductor substrate 1 formed with the field oxide film 2 is formed throughout with a first polycrystalline silicon film 3a of prescribed thickness by the chemical vapor deposition (CVD) process.
The surface of the first polycrystalline silicon film 3a is then added throughout with phosphorus, an impurity of N-type conductivity, by the ion implantation method to form a first polycrystalline silicon film 3a added with N-type impurity.
Next, annealing is effected in an oxygen atmosphere using an oxidation-diffusion furnace to form a memory oxide film 4 on the surface of the first polycrystalline silicon film 3a added with N-type impurity, as shown in FIG. 23.
Thereafter, as shown in FIG. 24, the surface of the memory oxide film 4 formed on the semiconductor substrate 1 is formed throughout with a second polycrystalline silicon film 3b of prescribed thickness by the CVD process.
The surface of the second polycrystalline silicon film 3b is added throughout with phosphorus, an impurity of N-type conductivity, by the ion implantation method to form a second polycrystalline silicon film 3b added with N-type impurity.
Next, the surface of the second polycrystalline silicon film 3b is spin-coated throughout with photoresist. The photoresist is exposed using a prescribed photomask and developed to pattern the photoresist 5 in the shape of a memory gate electrode 6, as shown in FIG. 25.
Dry etching using hydrogen bromide as etching gas is effected using the patterned photoresist 5 as an etching mask to pattern the second polycrystalline silicon film 3b shown in FIG. 24 into the memory gate electrode 6 shown in FIG. 25.
The semiconductor substrate 1 is thereafter immersed in a hydrofluoric acid aqueous solution to remove bromide occurring as a reaction product of the hydrogen bromide. The photoresist 5 is then removed.
Next, the surfaces of the first polycrystalline silicon film 3a and the memory gate electrode 6 are spin-coated throughout with photoresist. The photoresist is exposed using a prescribed photomask and developed to pattern the photoresist 5 in the shape of a gate electrode 7, as shown in FIG. 26.
Dry etching using hydrogen bromide as etching gas is effected using the patterned photoresist 5 as an etching mask to pattern the first polycrystalline silicon 3a as the gate electrode 7.
The semiconductor substrate 1 is thereafter immersed in a hydrofluoric acid aqueous solution to remove bromide occurring as a reaction product of the hydrogen bromide. The photoresist 5 is then removed.
Next, annealing is effected in an oxygen atmosphere using an oxidation diffusion furnace to form a memory mask oxide film 8 on the surfaces of the memory gate electrode 6 and the gate electrode 7, as shown in FIG. 27.
Following this, a silicon oxide film-type interlevel insulator 9 is formed over the whole surface by the CVD process so as to cover the memory mask oxide film 8.
The surface is spin-coated throughout with photoresist. The photoresist is exposed using a prescribed photomask and developed to pattern the photoresist 5 to form openings therein at locations where contact holes are to be formed, as shown in FIG. 28.
Isotropic etching is thereafter effected to pattern the interlevel insulator 9 at prescribed points (locations opposite the memory gate electrode 6 and the gate electrode 7), thereby forming contact holes 10.
Then, as shown in FIG. 29, metallic interconnections 11 composed of aluminum are formed through the contact holes 10 to complete an N-type inter-gate insulating film breakdown type memory.
Thus, as shown in FIG. 29, the conventional inter-gate insulating film breakdown type memory has the field oxide film 2 provided on the semiconductor substrate 1 and the gate electrode 7 provided on the field oxide film 2.
Further, the memory oxide film 4 is provided between the surface of the gate electrode 7 and the memory gate electrode 6 in the same region as the memory gate electrode 6.
A program can be written to this inter-gate insulating film breakdown type memory one time only by applying voltage to the memory gate electrode 6 to break down the memory oxide film 4.
Although the structure and method of fabricating an insulating film breakdown type memory whose gate electrode and memory gate electrode are of N-type conductivity (an N-type inter-gate insulating film breakdown type memory) was explained, the structure and fabrication of an insulating film breakdown type memory whose gate electrode and memory gate electrode are of P-type conductivity (a P-type inter-gate insulating film breakdown type memory) are substantially the same.
The change in current flow between the gate electrode 7 and the memory gate electrode 6 with voltage applied to the memory gate electrode 6 in the conventional inter-gate insulating film breakdown type memory of this type is shown by the graph of FIG. 31.
In FIG. 31, the horizontal axis represents voltage applied to the memory gate electrode 6 and the vertical axis represents current flow between the gate electrode 7 and the memory gate electrode 6. The broken line 13 indicates the breakdown voltage of the memory oxide film 4 and the one-dot chain line 14 indicates level of leak current allowable from the aspect of reliability.
Whether or not an inter-gate insulating film breakdown type memory of the type to which this invention relates has been programmed is judged from the value of the current between the gate electrode 7 and the memory gate electrode 6 relative to the voltage applied to the memory gate electrode 6.
The level of leak current allowable from the aspect of reliability referred to here indicates a level which does not result in an unprogrammed inter-gate insulating film breakdown type memory being judged as being programmed when a voltage lower than the programming voltage is applied to the memory gate electrode 6 for judging programmed/unprogrammed state.
As indicated by the characteristic of FIG. 31, in an inter-gate insulating film breakdown type memory fabricated by the conventional method explained with reference to FIGS. 21 to 29, the leak current exceeds the level allowable from the aspect of reliability at a low level of the voltage applied to the memory gate electrode 6 of around 2.5V.
An investigation of the cause for this revealed the following fact. For explaining this, an enlarged sectional view is shown in FIG. 30 of the boundary portion between the gate electrode 7 and the end portion of the memory gate electrode 6, the memory gate electrode 6 being that immediately after processing of the second polycrystalline silicon film 3b.
To secure a sufficient selectivity ratio with respect to the oxide film in the process of fabricating such an inter-gate insulating film breakdown type memory, dry etching of the memory gate electrode and the gate electrode is effected using hydrogen bromide (HBr) as the etching gas. Removal of the resulting bromide, produced as a reaction product, requires treatment with a hydrofluoric acid aqueous solution.
Because of this, as shown in FIG. 30, the thin memory oxide film 4 formed between the gate electrode 7 and the memory gate electrode 6, whose material is polycrystalline silicon, is etched laterally by the hydrofluoric acid aqueous solution, as indicated by the arrow E, simultaneously with its exposure.
The region where the memory oxide film 4 is laterally etched in this way is thereafter hard to form with a silicon oxide film possessing sufficient electrical insulating property either in the step shown in FIG. 27 of forming the memory mask oxide film 8 in an oxygen atmosphere using an oxidation diffusion furnace or in the step of forming the interlevel insulator 9 by the CVD process. In the worst case it remains as a cavity region.
Since this cavity region is present between the gate electrode 7 and the memory gate electrode 6 as a gap of only about several nm, it has poorer electrical insulating property than the region of the memory oxide film 4. As a result, unnecessary current flows between the gate electrode 7 and the memory gate electrode 6 merely by the application of a small voltage to the memory gate electrode 6, making normal operation as an inter-gate insulating film breakdown type memory extremely difficult to control.